1. Field of the Invention
The present invention relates to a method of fabricating a dynamic random access memory having an increased capacitance capacitor by incorporating a tub shape and by increasing the bottom electrode and top electrode overlap area.
2. Description of the Prior Art
In recent years there has been a dramatic increase in the packing density of DRAMs. Large DRAM devices are normally silicon based, and each cell typically embodies a single MOS field effect transistor with its source connected to a storage capacitor. This large integration of DRAMs has been accomplished by a reduction in individual cell size. However, the reduction in cell size results in a decrease in storage capacitance leading to reliability drawbacks, such as a lowering source/drain ratio and undesirable signal problems. In order to achieve the desired higher level of integration, the technology must keep almost the same storage capacitance on a greatly reduced cell area.
Efforts to maintain or increase the storage capacitance in memory cells with greater packing densities have included the use of a stacked capacitor design in which the capacitor cell uses the space over the device area for the capacitor plates. In their U.S. Pat. No. 5,053,351 to Fazan et al, the inventors describe a three-dimensional stacked capacitor which they call a stacked E cell. The storage node plate of this capacitor has an E-shaped cross-section. U.S. Pat. No. 4,742,018 to Kimura et al describes two separate embodiments of a stacked capacitor. The first embodiment provides for both top and bottom surfaces of the capacitor plate to be used for storage. The second embodiment provides sidewall structures for additional capacitance. Even higher capacitance can be achieved by incorporating a variety of techniques into one improved process.